Date: Nov 7, 2012 7:54 AM
Author: fl
Subject: Why there are two separate files in HDL verilog code and its testbench


I am using HDL Coder to generate verilog code. HDL Coder can also generate test bench. I find that HDL Coder generates two set of files for the synthesis code and test bench code on the filter components. This is different from my VHDL/verilog practice. I have compared the filter VHDL components for synthesis and test bench. There are some differences internally. HDL Coder can garantiee that the test bench and synthesis components are equivalent?