Date: May 17, 2013 4:34 AM
Subject: Overriding the single quote (')
The Verilog "programming" language provide a compact way to describe and work with digital circuits. The language features a nifty syntax for representing bits. For example 3'b101 is the 3 bit unsigned binary number 101. 3'd5 is the same binary number but represented as the decimal 5.
I wanted to set up an expression in Mathematica such as f[3'b101] rather than the more verbose f["3'b101"].
I thought I could simply set f to hold all its arguments using SetAttributes[f,HoldAll]. But FullForm[f[3'b101]] results in f[Times[Derivative, b101]].
I tried to "control the evaluation" using $PreRead and $Pre. I observed that Mathematica replaces the single-quote with Derivative sometime between $PreRead and $Pre. The closest I got to the solution is that I've managed to assign $PreRead a purefunction that will convert f[3'b101] to f["3'b101"]. (With 3'b101 as a string, Mathematica will not convert to Derivative.) But then, how do I set $Post to convert f["3'b101"] to f[3'b101]?
Does anyone know how to set Mathematica to avoid replacing single-quote with a Derivative under special circumstances?