Date: May 19, 2013 5:46 AM
Author: David Bailey
Subject: Re: Overriding the single quote (')

On 17/05/2013 09:34, Lawrence Walker wrote:
> The Verilog "programming" language provide a compact way to describe and work with digital circuits. The language features a nifty syntax for representing bits. For example 3'b101 is the 3 bit unsigned binary number 101. 3'd5 is the same binary number but represented as the decimal 5.
>
> I wanted to set up an expression in Mathematica such as f[3'b101] rather than the more verbose f["3'b101"].
>
> I thought I could simply set f to hold all its arguments using SetAttributes[f,HoldAll]. But FullForm[f[3'b101]] results in f[Times[Derivative[1][2], b101]].
>
> I tried to "control the evaluation" using $PreRead and $Pre. I observed that Mathematica replaces the single-quote with Derivative sometime between $PreRead and $Pre. The closest I got to the solution is that I've managed to assign $PreRead a purefunction that will convert f[3'b101] to f["3'b101"]. (With 3'b101 as a string, Mathematica will not convert to Derivative.) But then, how do I set $Post to convert f["3'b101"] to f[3'b101]?
>
> Does anyone know how to set Mathematica to avoid replacing single-quote with a Derivative under special circumstances?
>
> Thanks,
> Lawrence
>
>

On 17/05/2013 09:34, Lawrence Walker wrote:> The Verilog "programming"
language provide a compact way to describe and work with digital
circuits. The language features a nifty syntax for representing bits.
For example 3'b101 is the 3 bit unsigned binary number 101. 3'd5 is the
same binary number but represented as the decimal 5.
>
> I wanted to set up an expression in Mathematica such as f[3'b101]

rather than the more verbose f["3'b101"].
>
> I thought I could simply set f to hold all its arguments using

SetAttributes[f,HoldAll]. But FullForm[f[3'b101]] results in
f[Times[Derivative[1][2], b101]].
>
> I tried to "control the evaluation" using $PreRead and $Pre. I

observed that Mathematica replaces the single-quote with Derivative
sometime between $PreRead and $Pre. The closest I got to the solution
is that I've managed to assign $PreRead a purefunction that will convert
f[3'b101] to f["3'b101"]. (With 3'b101 as a string, Mathematica will
not convert to Derivative.) But then, how do I set $Post to convert
f["3'b101"] to f[3'b101]?
>
> Does anyone know how to set Mathematica to avoid replacing

single-quote with a Derivative under special circumstances?
>
> Thanks,
> Lawrence
>
>

If you want to process a language that is not Mathematica friendly, it
is probably best to store the text in a file, and read it in through a
simple parser written in Mathematica.

Alternatively, you could write a simple translator to take Verilog into
something more Mathematica friendly - perhaps 3'b101' could become "101"
or "b101" if there were no ambiguity with strings of other information.
You could pad with leading zeros if necessary to specify the bit length
- e.g. 5'b101 would be "b00101" .

My gut feeling is that fooling about with $Pre and $PreRead, etc. is a
recipe for wasting time handling too many gotcha's!

David Bailey
http://www.dbaileyconsultancy.co.uk