Drexel dragonThe Math ForumDonate to the Math Forum



Search All of the Math Forum:

Views expressed in these public forums are not endorsed by Drexel University or The Math Forum.


Math Forum » Discussions » Software » comp.soft-sys.matlab

Topic: Why there are two separate files in HDL verilog code and its testbench
Replies: 0  

Advanced Search

Back to Topic List Back to Topic List  
fl

Posts: 89
Registered: 10/8/05
Why there are two separate files in HDL verilog code and its testbench
Posted: Nov 7, 2012 7:54 AM
  Click to see the message monospaced in plain text Plain Text   Click to reply to this topic Reply

Hi,

I am using HDL Coder to generate verilog code. HDL Coder can also generate test bench. I find that HDL Coder generates two set of files for the synthesis code and test bench code on the filter components. This is different from my VHDL/verilog practice. I have compared the filter VHDL components for synthesis and test bench. There are some differences internally. HDL Coder can garantiee that the test bench and synthesis components are equivalent?

Thanks.



Point your RSS reader here for a feed of the latest messages in this topic.

[Privacy Policy] [Terms of Use]

© Drexel University 1994-2014. All Rights Reserved.
The Math Forum is a research and educational enterprise of the Drexel University School of Education.